Aluminum nitride substrate with graphite foil

ABSTRACT

A printed circuit board may include an aluminum nitride (AIN) substrate that includes an AIN thin film and a layer of high-frequency polymer as a carrier substrate of the AIN thin film. The AIN substrate forms a first layer of the printed circuit board. The AIN substrate comprises a heat spreader that laterally spreads out heat from a heat sink on the printed circuit board to form a thermal dissipation path parallel with a signal path on the printed circuit board. The printed circuit board may include a main substrate aligned to and bonded with the AIN substrate. The main substrate may include one or more additional layers of the printed circuit board.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a continuation application of U.S. application Ser. No. 14/680,719, entitled “ALUMINUM NITRIDE SUBSTRATE”, filed Apr. 7, 2015, which claims the benefit of U.S. Provisional Application No. 61/977,410, entitled “Printed Circuit Board Including Aluminum Nitride” filed Apr. 9, 2014, both of which are incorporated herein by reference in their entireties.

FIELD

Some embodiments described herein generally relate to printed circuit boards.

BACKGROUND

Unless otherwise indicated herein, the materials described herein are not prior art to the claims in the present application and are not admitted to be prior art by inclusion in this section.

Active heat loads such as active integrated circuits (ICs) may be mounted on top of heat sinks on a printed circuit board (PCB) and may generate heat during operation. Inefficient heat removal from the active loads may affect the performance of the active loads and/or the PCB. For example, in high-frequency applications (e.g., ≥25 gigabits per second), performance of the active loads and/or PCB may be degraded significantly if the heat is not removed efficiently. Existing technologies may rely on thermal vias to remove the heat in the z direction (e.g., orthogonal to the plane of the PCB). The vias are hollow holes filled with thermal conductive materials such as copper and may take up a substantial portion of space on the PCB. The vias may create bumps under the active loads and may also cause flatness issues. Signal routing on the PCB may be affected by the distribution of the vias on the PCB. Alternatively or additionally, existing technologies may use coining to create local thermal pools directly underneath the active loads and to remove the heat from the active loads. Coining may also interfere with signal paths on the PCB.

The subject matter claimed herein is not limited to embodiments that solve any disadvantages or that operate only in environments such as those described above. Rather, this background is only provided to illustrate one exemplary technology area where some embodiments described herein may be practiced.

BRIEF SUMMARY OF SOME EXAMPLE EMBODIMENTS

This Summary is provided to introduce a selection of concepts in a simplified form that are further described below in the Detailed Description. This Summary is not intended to identify key features or essential characteristics of the claimed subject matter, nor is it intended to be used as an aid in determining the scope of the claimed subject matter.

Some example embodiments described herein generally relate to techniques for constructing printed circuit boards.

In an example embodiment, a printed circuit board may include an aluminum nitride (AIN) substrate that includes an AIN thin film and a layer of high-frequency polymer as a carrier substrate of the AIN thin film. The AIN substrate may form a first layer of the printed circuit board. The AIN substrate may include a heat spreader that may laterally spread out heat from a heat sink on the printed circuit board to form a thermal dissipation path parallel with a signal path on the printed circuit board. The printed circuit board may include a main substrate aligned to and bonded with the AIN substrate. The main substrate may include one or more additional layers of the printed circuit board.

In another embodiment, an optical waveguide may include a layer of high-frequency polymer. The optical waveguide may include a first aluminum nitride (AIN) thin film disposed on top of the layer of high-frequency polymer. The first AIN thin film may include nitrogen content with a first nitrogen concentration level and a first index of refraction. The optical waveguide may include a second AIN thin film embedded in the first AIN thin film. The second AIN thin film may include nitrogen content with a second nitrogen concentration level and a second index of refraction. The first nitrogen concentration level may be lower than the second nitrogen concentration level. The first index of refraction may be lower than the second index of refraction. The second AIN thin film may be embedded in the first AIN thin film to guide a light beam to propagate through the second AIN thin film.

Additional features and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by the practice of the invention. The features and advantages of the invention may be realized and obtained by means of the instruments and combinations particularly pointed out in the appended claims. These and other features of the present invention will become more fully apparent from the following description and appended claims, or may be learned by the practice of the invention as set forth hereinafter.

BRIEF DESCRIPTION OF THE DRAWINGS

To further clarify the above and other advantages and features of the present invention, a more particular description of the invention will be rendered by reference to specific embodiments thereof which are illustrated in the appended drawings. It is appreciated that these drawings depict only typical embodiments of the invention and are therefore not to be considered limiting of its scope. The invention will be described and explained with additional specificity and detail through the use of the accompanying drawings in which:

FIGS. 1A-5 are block diagrams illustrating cross-sectional views of stack-ups of various example aluminum nitride (AIN) substrates;

FIG. 6A is a graphical representation illustrating a side view of an alignment of an example AIN substrate and an example main substrate;

FIG. 6B is a graphical representation illustrating a top view of the alignment of the example AIN substrate and the example main substrate of FIG. 6A;

FIG. 7 is a block diagram illustrating a cross-sectional view of a stack-up of an example printed circuit board including an example AIN substrate and an example main substrate bonded using pre-impregnated composite film materials (PRE-PREG);

FIG. 8 is a block diagram illustrating a cross-sectional view of a stack-up of another example printed circuit board including an example AIN substrate and an example main substrate bonded using a thermosetting conductive bonding film;

FIG. 9 is a block diagram illustrating a cross-sectional view of a stack-up of yet another example printed circuit board;

FIG. 10 is a block diagram illustrating a stack-up of example wave guides in an example printed circuit board;

FIG. 11A is a block diagram illustrating a top view of an example chip-to-chip optical communication routing through a waveguide;

FIG. 11B is a block diagram illustrating a side view of the example chip-to-chip optical communication routing through the waveguide of FIG. 11A;

FIG. 12A is a block diagram illustrating a cross-sectional view of a waveguide formed by an example AIN substrate;

FIG. 12B is a block diagram illustrating another cross-sectional view of the waveguide of FIG. 12A that routes a light beam from a laser to a photodiode;

FIG. 12C is a graphic representation illustrating a simulation of light transmission through the waveguide of FIGS. 12A and 12B;

FIG. 13 is a block diagram illustrating a cross-sectional view of an example etched Bragg grating;

FIG. 14 is a block diagram illustrating an example wavelength division multiplexing (WDM) device that includes distributed Bragg reflectors formed by etched Bragg gratings similar or identical to the etched Bragg grating of FIG. 13;

FIG. 15 is a graphic representation illustrating an example relationship between a transmission rate and an index of refraction for Aluminum nitride;

FIG. 16 is a graphic representation illustrating example effective permittivity curves for a circuit stack-up;

FIG. 17A is a graphic representation illustrating an example thermal scan of a heat load on a kapton side;

FIG. 17B is a graphic representation illustrating an example thermal scan of a heat load on an AIN substrate;

FIG. 17C is a graphic representation illustrating an example thermal scan of a heat load on a flame retardant four (FR4) substrate of a PCB;

FIG. 17D is a graphic representation illustrating an example thermal scan of a heat load on a silver-plated PCB substrate;

FIG. 17E is a graphic representation illustrating an example thermal scan of a heat load on an AIN substrate;

FIG. 18 is a graphic representation illustrating example relationship between photon energy and an absorption coefficient for Aluminum nitride; and

FIG. 19 is a graphic representation illustrating example relationship between an index of refraction and a wavenumber and example relationship between an absorption index and the wavenumber for Aluminum nitride.

DETAILED DESCRIPTION OF SOME EXAMPLE EMBODIMENTS

Embodiments described herein generally relate to techniques for constructing printed circuit boards (PCBs) using aluminum nitride (AIN).

Some embodiments described herein may include an AIN substrate formed by an AIN thin film on a layer of high-frequency polymer. The layer of high-frequency polymer may include polyimide, kapton, amorphous glass, or another suitable type of dielectric material. For example, the AIN substrate may include an AIN thin film in a polycrystalline form deposited on a thin layer of polyimide, kapton or any other suitable bonding material. The AIN thin film may include dielectric material with a higher lateral and/or vertical thermal conductivity compared to other dielectric materials such as glass reinforced dielectric materials (e.g., FR-4 or PRE-PREG materials). For example, the AIN dielectric material may have a thermal conductivity between 4 watts per meter kelvin (W/m-K) and 10 W/m-K. In comparison, a thermal conductivity of some regular dielectric materials may be about 0.2-0.3 W/m-K. In some embodiments, better homogeneity may be achieved using AIN dielectric material compared to using other dielectric materials including fiber glass weaves. The AIN substrate may be used to form a top layer, a bottom layer, a core layer, or another selected layer of a PCB.

The AIN substrate may be in a flexible form and may include a thickness between 10 micrometers and 100 micrometers. The AIN substrate may be constructed using various deposition techniques including, but not limited to, direct current (DC) reactive magnetic sputtering, plasma vapor deposition, chemical vapor deposition, plasma immersion ion implantation, and any other suitable type of deposition technique.

Metallization of the AIN substrate may be implemented through metallization deposition techniques, yielding smooth and even metal patterns on surfaces of the AIN substrate. Example metallization deposition techniques may include, but are not limited to, titanium (Ti)/Ti silicon nitride (SiN)/gold (Au), Ti/platinum (Pt)/Au, Ti-Tungstent (W)/Au, chromium-copper (Cr—Cu), Cr—Au, Ti—W/nickel (Ni)—Cu, TaN—Cr—Au, Ti-palladium (Pd)—Au, molybdenum (Mo)-manganese (Mn), eletro less copper, silver, electro less titanium electro less palladium immersion gold (ETIG), and deposition using other suitable metals or metal alloys.

The AIN substrate may be transparent and may be surrounded by dielectric material with a permittivity (or, an index of refraction) lower than AIN, so that the aluminum substrate may form an optical waveguide. Thus, chip-to-chip optical communication may be routed through the AIN substrate.

The AIN substrate may be sufficiently thin (e.g., with a thickness no greater than 30 micrometers such as 15 micrometers, 20 micrometers, or 25 micrometers) and may have high quality microwave capability (e.g., high dielectric constant (e.g., Dk>6) and low dissipation factor (e.g., Df<0.01)). If the AIN substrate forms a top layer and/or a bottom layer of a PCB, traces and/or transmission lines with super fine geometries may be deposited on a top side and/or a bottom side of the PCB for massive parallel photonic circuit architectures. For example, pairs of micro strip lines with a trace width of about 10 micrometers to 65 micrometers and a trace pitch width of about 15 micrometers to 200 micrometers may be deposited on the top side and/or the bottom side of the PCB.

In some embodiments, the AIN substrate may be bonded to a main substrate to form a PCB. The AIN substrate may include an AIN thin film that may be deposited on a thin layer of polyimide, kapton, or any other suitable bonding material. The main substrate may adhere to the AIN substrate and may include PRE-PREG layers, metal layers, layers of polyimide or kapton, and other circuit board layers. The PCB may include a rigid board or a flexible board. The main substrate may include one or more circuit board layers. The AIN substrate may be aligned with the main substrate using fiducial alignment. The AIN substrate and its electrically conductive vias may be bonded to the main substrate using one or more of: (1) wafer scale thermal compression bonding; (2) a PCB PRE-PREG attaching process; (3) a thermosetting conductive bonding film such as CBF-300 or another suitable type of bonding film; (4) backfilling through vias on the main substrate with electro-deposited copper to form contact with vias on the AIN substrate; and (5) other suitable bonding techniques. Alternatively, the AIN substrate may be bonded to kapton or may stand by itself so that a layer of high-frequency polymer (e.g., polyimide) may hold the AIN substrate together.

The construction of a PCB with an AIN substrate may improve heat dissipation in the PCB compared to using other dielectric materials such as dielectric materials with fiber glass weaves. The AIN substrate may act as a thermal heat spreader to provide a wider area for heat dissipation compared to using coining and may allow heat to flow laterally in the x-y directions (e.g., in the plane of the PCB). Thus, heat may be spread efficiently in the x-y directions by the AIN substrate as well as in the z-direction using vias. Lateral heat flow provided by a heat spreader layer that includes an AIN substrate may be beneficial for heat removal and/or heat dissipation in the PCB.

Example applications of the AIN substrates described herein may include combining the AIN substrates with flexible electronic devices including integrated circuits (ICs) made of amorphous silicon, organic semiconductor(s) and/or graphene. The flexible electronic devices may include wearable electronic devices such as smart watches, wrist-band activity tracking devices, and/or any other wearable devices.

With reference to detailed description provided below, example advantages of the AIN substrate will be more obvious. For example, the AIN substrate may be in a flexible foil form. The AIN substrate may have a higher lateral and/or vertical thermal conductivity (e.g., K>4 or 10 W/m-k) than standard dielectric core or PRE-PREG materials, and may act as an efficient thermal heat spreader. The AIN substrate may be capable of implementing high isolation microwave circuitry and/or optical devices on a PCB architecture without laminates such as high-temperature co-fired ceramics (HTCC) or low-temperature co-fired ceramics (LTCC). The AIN substrate may make 100% flip chip bondable mixed signal and/or optical daughter (or mother) substrate on a PCB (or a flex circuitry) to be possible. The PCB may be a flex, semi-rigid, or rigid PCB. The AIN substrate may eliminate use of expensive laminate microwave substrates and utilize a PCB architecture with use of a sequential lamination of polycrystalline AIN and polyimide. The AIN substrate may be a flexible multi-purpose AIN and polyimide substrate and may be environmentally robust with flexural strength.

For example, the AIN substrate does not include fiber weave or glass weave and may be utilized to form fine or super fine transmission lines (e.g., with a width <50 micron, an impedance of 50 or 100 ohms) and 50 G controlled impedance lines. The AIN substrate may form surface-mount technology (SMT) assembly with copper, gold, silver, nickel, or palladium based metallization. The palladium based metallization may be used to improve durability and wire bonding.

For example, the AIN substrate may form an optical waveguide, an optical grating, or an optical prism with an AIN (or AINx) trench waveguide and onboard grating architecture. The AIN substrate may be 85%-90% transparent for wavelengths between 850 nanometers and 1550 nanometers. The optical attenuation may be controllable. In some embodiments, optical routers, multiplexers, and/or demultiplexers may be fabricated on flexible AIN or aluminum oxide (Al₂O₃) substrate, with trench or ridge waveguides formed with AIN or Al₂O₃.

For example, implementation of the AIN substrate is compatible with existing processes (e.g., sequential lamination processes, laser drilling processes, various metallization processes). The AIN substrate may be easy to drill and cut. The AIN substrate may allow for reduction and non-invasive substrate development without massive thermal vias and restricted routing.

Reference will now be made to the drawings to describe various aspects of some example embodiments of the invention. The drawings are diagrammatic and schematic representations of such example embodiments, and are not limiting of the present invention, nor are they necessarily drawn to scale.

FIG. 1A is a block diagram illustrating a cross-sectional view of a stack-up of an example AIN substrate 100, arranged in accordance with at least some embodiments described herein. The example AIN substrate 100 may include an AIN thin film 102, a layer of high-frequency polymer 104, and a layer of cladding copper 106. In some embodiments, the high-frequency polymer 104 may include one of polyimide, kapton, amorphous glass, and any other type of suitable high-frequency dielectric material. The cladding copper 106 may include a plating of copper cladded on the high-frequency polymer 104. For example, the high-frequency polymer 104 and the cladding copper 106 may form a commercial copper-plated polyimide layer or roll.

In some embodiments, the AIN thin film 102 may be deposited on the high-frequency polymer 104 using various deposition methods including, but not limited to, reactive magnetron sputtering, pulsed DC magnetic sputtering, plasma vapor deposition, chemical vapor deposition, plasma immersion ion implantation, and any other suitable deposition method.

The AIN thin film 102 may include AIN dielectric material with a higher lateral and/or vertical thermal conductivity than other dielectric materials such as flame retardant four (FR-4) or PRE-PREG materials. In these and other embodiments, the AIN dielectric material may have a thermal conductivity of at least 4 W/m-K. For example, AIN may have a thermal conductivity between 4 W/m-K and 10 W/m-K while a thermal conductivity of regular dielectric material may be between 0.2 W/m-K and 0.3 W/m-K. The AIN thin film 102 may have high dielectric constant (e.g., Dk>6) and low dissipation factor (e.g., Df<0.02 or 0.03) compared to other dielectric materials such as FR-4 or PRE-PREG materials.

The AIN thin film 102 may include nitrogen content with a particular nitrogen concentration level. A higher nitrogen concentration level in the AIN thin film 102 may result in a higher roughness in the AIN thin film 102 (e.g., a roughness in a micron level). The AIN thin film 102 does not include fiber weaves or glass weaves that are commonly included in FR-4 or PRE-PREG materials.

In some embodiments, the AIN substrate 100 of FIG. 1A and/or other AIN substrates described herein may be used to form a core layer, a top layer, a bottom layer, and/or a selected layer of a PCB. The AIN substrate may be bonded with other circuit board layers to form a PCB. For example, a stack-up of the PCB may include: (1) a top layer including differential micro strip pairs; (2) a layer including return path ground; (3) a layer formed by an AIN substrate; (4) one or more additional inner layers for low-to-mid speed routing; (5) another layer formed by another AIN substrate; (6) another layer including return path ground; and (7) a bottom layer including differential micro strip pairs. The return path grounds may be continuous and may cover part of or full area of the substrates. The AIN substrates may cover part of or full area of the substrate. Some example PCBs according to some embodiments are illustrated in and described with reference to FIGS. 7-9.

The AIN substrate 100 of FIG. 1A and/or other AIN substrates described herein may form a flexible foil and may include a thickness between 10 and 100 micrometers, such as a thickness of 15 micrometers, 20 micrometers, or 25 micrometers. In other embodiments, the AIN substrate 100 of FIG. 1A and/or other AIN substrates described herein may include a thickness greater than 100 micrometers or less than 10 micrometers. For example, the AIN substrate 100 may include the AIN thin film 102 with a thickness of 13 micrometers disposed on a polyimide foil with a thickness of 25 micrometers.

Because the AIN substrate 100 of FIG. 1A and/or other AIN substrates described herein may be sufficiently thin (e.g., with a thickness no greater than 30 micrometers such as 15 micrometers, 20 micrometers, or 25 micrometers) and may have high quality microwave capability (e.g., high dielectric constant (e.g., Dk>6) and low dissipation factor (e.g., Df<0.01, 0.02, or 0.03)) compared to glass-reinforced dielectric materials, traces and/or transmission lines with super fine geometries may be deposited on a top side and/or a bottom side of the PCB for massive parallel photonic circuit architectures. For example, an AIN substrate may form a top layer of the PCB, and a top side of the PCB may include traces with a width of about 10 micrometers to 65 micrometers and trace pitches with a width of about 15 micrometers to 200 micrometers. Coplanar micro strip or other micro strip pairs each formed by two traces may include a differential impedance of about 100 ohms. As used herein, the term “about” as applied to a value may indicate a range of ±10% of the stated value. Alternatively or additionally, another AIN substrate may form a bottom layer of the PCB, and a bottom side of the PCB may include traces with a width of about 10 micrometers to 65 micrometers and trace pitches with a width of about 15 micrometers to 200 micrometers. Micro strip pairs each formed by two traces may include a differential impedance of about 100 ohms. In these and other embodiments, the traces and trace pitches may have other dimensions not described herein.

Because of the super fine geometries of the traces and/or transmission lines, the PCB may be configured to operate at a transmission speed of about 25 gigabits per second per channel or a transmission speed higher than 25 gigabits per second per channel (e.g., 28 gigabits per second per channel, 50 gigabits per second per channel). It may be easy to laser drill and/or cut the AIN substrate. The AIN substrate may be optically transparent and may be used to form various photonic waveguide structures along with flip chip active photonic devices. Thus, chip-to-chip optical communication may be routed through the AIN based waveguide on board the substrate. An example waveguide formed by AIN is illustrated in FIGS. 11A and 11B. Although some embodiments are described as facilitating or involving transmission speeds of 25 gigabits per second or higher, the embodiments may also be used with transmission speeds lower than 25 gigabits per second.

FIG. 1B is a block diagram illustrating a cross-sectional view of a stack-up of another example AIN substrate 150, arranged in accordance with at least some embodiments described herein. Compared to the AIN substrate 100 of FIG. 1A, the high-frequency polymer 104 of the AIN substrate 150 may be disposed on top of the AIN thin film 102 so that the AIN thin film 102 may be disposed between the cladding copper 106 and the high-frequency polymer 104.

FIG. 2 is a block diagram illustrating a cross-sectional view of a stack-up of an example AIN substrate 200 with metallization, arranged in accordance with at least some embodiments described herein. The AIN substrate 200 may be metallized through deposition techniques, yielding smooth and even metal patterns and/or traces. The metals or metal alloys used in the metallization of the AIN substrate may include, but are not limited to, Ti/Ti SiN/Au, Ti/Pt/Au, Ti—W/Au, Cr—Cu, Cr—Au, Ti—W/Ni—Cu, TaN—Cr—Au, Ti—Pd—Au, Mo—Mn, electrodes copper, and other suitable metals or metal alloys.

The example AIN substrate 200 illustrated in FIG. 2 may include one or more of a layer of cladding copper 206, a layer of high-frequency polymer 204, an AIN thin film 202, a first patterned mask 208 a, a layer of metal deposition 210, a layer of electrolytic copper 212, a second patterned mask 208 b, and a plating 214. The cladding copper 206, the high-frequency polymer 204, and the AIN thin film 202 may be similar to the cladding copper 106, the high-frequency polymer 104, and the AIN thin film 102 of FIG. 1A, respectively. The description for similar elements already described above will not be repeated here.

In some embodiments, the metal deposition 210 may include one of Ni-chrome-electro-vaccum deposition, Tin palladium colloid electro less deposition, Ni—P electro less deposition, and any other suitable type of metal deposition. The electrolytic copper 212 may be plated over a Ni-chrome patterned surface if the metal deposition 210 includes Ni-chrome-electro-vacuum deposition. Similarly, the electrolytic copper 212 may be plated over a Tin palladium colloid patterned surface if the metal deposition 210 includes Tin palladium colloid electro less deposition. The electrolytic copper 212 may be plated over a Ni—P patterned surface if the metal deposition 210 includes Ni—P electro less deposition.

The plating 214 may include electro less nickel electro less palladium immersion gold (ENEPIG) or any other suitable type of plating. In some embodiments, the plating 214 may include palladium with a sufficient thickness that enables a PCB including the AIN substrate 200 to pass corrosion tests such as a mixed flowing gas test. For example, a thickness of the palladium used herein may be about 0.5 micrometers or more, rather than a thickness between 0.03 micrometers and 0.3 micrometers used in some other PCBs.

One or more vias 224 a, 224 b, 224 c, 224 d, and 224 e may be drilled in the AIN substrate 200 using laser or other hole drilling techniques. The vias 224 a-224 e may include copper filled vias. The vias 224 a-224 e each may have a diameter greater than 25 micrometers. In these and other embodiments, the vias 224 a-224 e may have other dimensions different from those described herein. Although the vias 224 a-224 e are illustrated as through holes (or through vias) in the AIN substrate 200, the vias 224 a-224 e may include blind vias and/or buried vias in some embodiments. Although five vias 224 a-224 e are illustrated in FIG. 2, the AIN substrate 200 may include any number of vias in some embodiments.

In some embodiments, the AIN substrate 200 of FIG. 2 and/or other AIN substrates described herein may be constructed by performing operations including one or more of the following: (1) applying a mask pattern to an AIN thin film for deposition of an adhesion layer; (2) performing an etching process to etch away excess adhesion layer metal; (3) masking pattern for copper deposition (including fiducial marks and/or alignment holes); (4) drilling holes for via placement using laser or other drilling techniques; (5) depositing electrolytic copper onto the adhesion layer; (6) making pattern for copper etch; and (7) performing deposition of ENEPIG. In these and other embodiments, different and/or additional operations may be performed to construct the AIN substrate.

FIG. 3 is a block diagram illustrating a cross-sectional view of a stack-up of another example AIN substrate 300 with metallization, arranged in accordance with at least some embodiments described herein. The metallization of the AIN substrate 300 may be performed using deposition techniques as described herein. The AIN substrate 300 may include one or more of a plating 314, a patterned mask 308 c, electrolytic copper 312, a patterned mask 308 b, metal deposition 310 b, an AIN thin film 302, metal deposition 310 a, a patterned mask 308 a, a layer of high-frequency polymer 304, and a layer of cladding copper 306. Description for similar elements already described above will not be repeated here.

Five vias 334 a, 334 b, 334 c, 334 d, and 334 e are illustrated by way of example in FIG. 3. The vias 334 a-334 e may include copper filled vias. Although the vias 334 a-334 e are illustrated as through holes in the AIN substrate 300, the vias 334 a-334 e may include blind vias and/or buried vias in some embodiments. Although five vias 334 a-334 e are illustrated in FIG. 3, the AIN substrate 300 may more generally include any number of vias.

FIG. 4 is a block diagram illustrating a cross-sectional view of a stack-up of yet another example AIN substrate 400 with metallization, arranged in accordance with at least some embodiments described herein. The metallization of the AIN substrate 400 may be performed using deposition techniques described herein. The AIN substrate 400 may include one or more of a plating 414 b, a patterned mask 408 d, electrolytic copper 412 b, a patterned mask 408 b, metal deposition 410 b, an AIN thin film 402, metal deposition 410 a, a patterned mask 408 a, electrolytic copper 412 a, a patterned mask 408 c, a plating 414 a, a layer of high-frequency polymer 404, and a layer of cladding copper 406. Description for similar elements already described above will not be repeated here. Four vias 444 a, 444 b, 444 c, and 444 d are illustrated by way of example in FIG. 4. The vias 444 a-444 d may include copper filled vias. More generally, the AIN substrate 400 may include any number and/or any types of vias.

FIG. 5 is a block diagram illustrating a cross-sectional view of a stack-up of an example double sided AIN substrate 500 with metallization, arranged in accordance with at least some embodiments described herein. The metallization of the AIN substrate 500 may be performed using deposition techniques described herein. The AIN substrate 500 may include one or more of a plating 514 a, a patterned mask 508 c, electrolytic copper 512 a, metal deposition 510 a, a patterned mask 508 a, an AIN thin film 502 a, a first layer of high-frequency polymer 504 a, a second layer of high-frequency polymer 504 b, an AIN thin film 502 b, a patterned mask 508 b, metal deposition 510 b, electrolytic copper 512 b, a patterned mask 508 d, and a plating 514 b. The first layer of high-frequency polymer 504 a and the second layer of high-frequency polymer 504 b may act as bonding layers to bond the AIN thin films 502 a and 502 b together. Description for similar elements already described above will not be repeated here. Three vias 535 a, 535 b, and 535 c are illustrated by way of example in FIG. 5. The vias 535 a-535 c may include copper filled vias. More generally, the AIN substrate 500 may include any number and/or any types of vias.

FIG. 6A is a graphical representation illustrating a side view of an alignment of an example AIN substrate 602 and an example main substrate 604, arranged in accordance with at least some embodiments described herein. The AIN substrate 602 may include any of the AIN substrates 100, 150, 200, 300, 400, and/or 500 illustrated in FIGS. 1A-5. The AIN substrate 602 may include fiducial markers such as fiducial holes 606 a and 606 b. The main substrate 604 may include one or more circuit board layers such as an internal layer, a bottom layer, a PREPREG layer, and/or a core layer. The main substrate 604 may include fiducial markers such as fiducial holes 608 a and 608 b. The AIN substrate 602 may be aligned with the main substrate 604 using the fiducial holes. For example, the fiducial hole 606 a may be aligned to the fiducial hole 608 a, and the fiducial hole 606 b may be aligned to the fiducial hole 608 b. In some embodiments, a micrometer-scale alignment resolution may be achieved. In these and other embodiments, the AIN substrate 602 may be aligned to the main substrate 604 using other approaches instead of or in addition to the fiducial alignment.

The AIN substrate 602 may be bonded with the main substrate 604 to form a PCB such as a rigid board or a flexible board. For example, the AIN substrate 602 may be bonded with the main substrate 604 so that the AIN substrate 602 may form a top layer of the PCB while the main substrate 604 may form a remainder of the PCB. In these and other embodiments, the AIN substrate 602 may form any other layer of the PCB such as a bottom layer, a core layer, or other selected layer.

FIG. 6B is a graphical representation illustrating a top view of the alignment of the example AIN substrate 602 and the example main substrate 604 of FIG. 6A, arranged in accordance with at least some embodiments described herein. In FIG. 6B, the fiducial hole 606 a of the AIN substrate 602 may be aligned with the fiducial hole 608 a of the main substrate 604. The fiducial hole 606 b of the AIN substrate 602 may be aligned with the fiducial hole 608 b of the main substrate 604. A fiducial hole 606 c of the AIN substrate 602 may be aligned with a fiducial hole 608 c of the main substrate 604. A fiducial hole 606 d of the AIN substrate 602 may be aligned with a fiducial hole 608 d of the main substrate 604. Although the AIN substrate 602 and the main substrate 604 are described as including four fiducial holes 606 d-606 d or 608 a-608 d each, more generally, each of the AIN substrate 602 and the main substrate 604 may include two or more fiducial holes.

FIG. 7 is a block diagram illustrating a cross-sectional view of a stack-up of an example PCB 700 including an example AIN substrate 730 and an example main substrate 732 bonded together using PRE-PREG, arranged in accordance with at least some embodiments described herein. The AIN substrate 730 may include one or more of a plating 714, a patterned mask 708 c, electrolytic copper 712, a patterned mask 708 b, metal deposition 710 b, an AIN thin film 702, metal deposition 710 a, a layer of high-frequency polymer 704, a layer of cladding copper 706, and a patterned mask 708 a. Description for similar elements already described above will not be repeated here. In some embodiments, the AIN substrate 730 may include any of the AIN substrates 100, 150, 200, 300, 400, 500 illustrated in FIGS. 1A-5. The main substrate 732 may include one or more circuit board layers 722 a-722 n, such as a core (FR-4 or Megtron VI), a layer of PRE-PREG, and/or a bottom layer.

In these and other embodiments, a layer of PRE-PREG 720 a may be included in the AIN substrate 730. A layer of PRE-PREG 720 b may be included in the main substrate 732. The main substrate 732 may be bonded with the AIN substrate 730 using the PRE-PREGs 720 a and 720 b through an adhesion process performed after an etch process. A via 734 in the AIN substrate 730 may be thermally coupled with a via 736 in the main substrate 732. The vias 734 and 746 may include copper filled vias. Although one via 734 in the AIN substrate 730 and one via 736 in the main substrate 732 are illustrated in FIG. 7, more generally the AIN substrate 730 may include one or more vias 734 thermally coupled to one or more corresponding vias 736 in the main substrate 732.

FIG. 8 is a block diagram illustrating a cross-sectional view of a stack-up of another example PCB 800 including an example AIN substrate 830 and an example main substrate 832 bonded using a thermosetting conductive bonding film 820, arranged in accordance with at least some embodiments described herein.

The AIN substrate 830 may include one or more of a plating 814, a patterned mask 808 c, electrolytic copper 812, a patterned mask 808 b, metal deposition 810 b, an AIN thin film 802, metal deposition 810 a, a layer of high-frequency polymer 804, a layer of cladding copper 806, and a patterned mask 808 a. Description for similar elements already described above will not be repeated here. In some embodiments, the AIN substrate 830 may include any of the AIN substrates 100, 150, 200, 300, 400, 500 illustrated in FIGS. 1A-5.

The main substrate 832 may include one or more circuit board layers 822 a-822 n, such as a top layer, a core (FR-4 or Megtron VI), a layer of PRE-PREG, and/or a bottom layer. The main substrate 832 may be bonded with the AIN substrate 830 using the thermosetting conductive bonding film 820. In some embodiments, the thermosetting conductive bonding film 820 may include CBF-300 or another suitable type of bonding film. The thermosetting conductive bonding film 820 may include a conductive path 838 for thermally coupling a via 834 in the AIN substrate 830 to a via 836 in the main substrate 832. The vias 834 and 846 may include copper filled vias. Although one via 834 in the AIN substrate 830, one via 836 in the main substrate 832, and one conductive path 838 in the thermosetting conductive bonding film 820 are illustrated in FIG. 8, more generally the AIN substrate 830 may include one or more vias 834 thermally coupled to one or more corresponding vias 836 in the main substrate 832 using one or more conductive paths 838 in the thermosetting conductive bonding film 820.

FIG. 9 is a block diagram illustrating a cross-sectional view of a stack up of yet another example PCB 900, arranged in accordance with at least some embodiments described herein. The PCB 900 may include a rigid board or a flexible board. The PCB 900 may include a heat sink 902, a coverlay/solder mask 904, another heat sink 903, a metal layer 906, a core 908, a metal layer 910, a layer of high-frequency polymer 912, a graphite foil 914, a core 916, another graphite foil 918, another layer of high-frequency polymer 920, a metal layer 922, a heat paddle 924, another coverlay/solder mask 926, another heat paddle 928, and other suitable elements. In these and other embodiments, the PCB 900 may include vias 930, 932, 934, 936, 938, 940, and 942 (collectively “vias 930-942”). Although seven vias 930-942 are illustrated as blind vias in FIG. 9, more generally the PCB 900 may include any number of blind vias, through vias, and/or buried vias.

In some embodiments, the core 908 may include aluminum nitride. Alternatively or additionally, the core 916 may include aluminum nitride. The layers of high-frequency polymer 912 and 920 may include polyimide, kapton, or another suitable type of dielectric material coated with silicon nitride (SiN), silicon oxide (SiOx), amorphous silicon (a-Si), or another suitable type of coating material, with a coating thickness of about 100 micrometers. The graphite foils 914 and 918 may include a thermal conductivity no less than 300 W/m-K in the x-y directions and 15 W/m-K in the z direction. The graphite foils 914 and 918 may thus be highly thermally conductive compared to the AIN. In some embodiments, the layer of high-frequency polymer 912 and the graphite foil 914 may form a heat spreader layer 950. Alternatively or additionally, the layer of high-frequency polymer 920 and the graphite foil 918 may form another heat spreader layer 952. In these and other embodiments, the cores 908 and 916 including AIN may also act as heat spreader layers which may allow lateral heat flow.

In some embodiments, active loads (e.g., active integrated circuits) may be mounted on the heat sinks 902 and 903. Heat generated by the active loads may be drawn away from the heat sinks 902 and 903 to the heat spreader layers 950 and 952 and also to the heat paddles 924 and 928 through the vias 930-942. Heat extraction described herein may be spread across the PCB 900 using the heat spreader layers 950 and 952, the cores 908 and 916, and/or the metal layers 906 and 922, rather than being localized directly underneath the active load. Lateral heat flow on the heat spreader layers 950 and 952 may be beneficial for heat removal and/or heat distribution.

With combined reference to FIGS. 1A-10 described above, some embodiments described herein may include a semi-rigid or flexible double-sided multi-layer PCB that may be sequentially laminated and suitable for wire bonding and surface mount assembly. The PCB may include: an AIN substrate that includes an AIN thin film and a layer of high-frequency polymer (e.g., polyimide, kapton, or another suitable type of materials) as a carrier substrate of the AIN thin film; and a main substrate aligned to and bonded with the AIN substrate. The main substrate may include one or more additional layers of the PCB. The AIN substrate may be configured to form one of a top layer, a bottom layer, and a core layer of the PCB.

The AIN substrate may be configured as a heat spreader that laterally spreads out heat from a heat sink on the PCB so that a thermal dissipation path may be formed to be parallel with a signal path on the PCB. For example, a signal path on the PCB may be parallel with an x-y plane (e.g., a plane of the PCB or the AIN substrate), and heat may be laterally spread out across the x-y plane of the AIN substrate in addition to a vertical direction (z direction) spread. The heat dissipation is not localized directly underneath the active load. Different from a copper coin which may wipe out trace routing space in an area (e.g., due to construction of inter-layer vias which obstruct routing space in subsequent layers), the heat dissipation of the AIN substrate does not create holes inside the PCB and therefore avoids loss of routing space within the PCB.

The PCB further includes a thermosetting conductive bonding film that bonds the AIN substrate to the main substrate. The AIN substrate may include a first via, the main substrate may include a second via, and the thermosetting conductive bonding film may include a conductive path that may electrically and/or thermally couple the first via with the second via. The conductive path may be electrically conductive only in a vertical direction (z direction), allowing via transitioning from the first via to the second via.

In some embodiments, the AIN thin film may include nitrogen content with a particular nitrogen concentration level and may be free of fiber weave materials or glass weave materials. The AIN substrate may include a low loss tangent that is lower than that of fiber weave materials. For example, the loss tangent of the AIN substrate may be lower than 0.04. The AIN substrate may include a thickness between 1 micrometer and 100 micrometers.

In some embodiments, the AIN substrate may form a top layer of the PCB with a thickness no greater than 150 micrometers, and a top side of the PCB may include traces with a width between about 10 micrometers and about 65 micrometers and trace pitches with a width between about 15 micrometers and 200 micrometers.

The AIN substrate may include a metallization of one of nickel (Ni)-based deposition, palladium-based deposition, silver-based deposition, Ni-chrome-electro-vacuum deposition, Tin palladium colloid electro less deposition, and Ni—P electro less deposition. The silver-based metallization may be applied in high frequency where skin depth issues prevent usage of nickel. The palladium-based metallization may be applied in wire bonding or other situations to improve durability.

FIG. 10 is a block diagram illustrating a stack-up of example wave guides in an example PCB 1000, arranged in accordance with at least some embodiments described herein. The example PCB 1000 may include, among others, a waveguide 1016 a, one or more cores 1012, including cores 1012 a, 1012 b, and 1012 c, and another waveguide 1016 b. The waveguide 1016 a may include a metal layer 1002 a, an AIN thin film 1004 a, a bonding layer 1006 a, another AIN thin film 1004 b, and another metal layer 1002 b. The waveguide 1016 a may form a top layer of the PCB. The bonding layer 1006 a may include polyimide, kapton, or another suitable type of bonding material. The cores 1012 a, 1012 b, and 1012 c may include FR-4, Megtron VI, or another suitable type of cores. The waveguide 1016 b may include a metal layer 1002 c, an AIN thin film 1004 c, a bonding layer 1006 b, another AIN thin film 1004 d, and another metal layer 1002 d. The waveguide 1016 b may form a bottom layer of the PCB. The bonding layer 1006 b may include polyimide, kapton, or another suitable type of bonding material. Optical communication routing may be implemented through the waveguide 1016 a and/or the waveguide 1016 b.

FIG. 11A is a block diagram illustrating a top view of an example chip-to-chip optical communication routing through a waveguide 1100, arranged in accordance with at least some embodiments described herein. The waveguide 1100 may be formed by an AIN thin film 1106 surrounded by dielectric material 1104 having a permittivity (or an index of refraction) lower than the aluminum nitride. Example dielectric material 1104 may include metal, air, or another type of dielectric material with an index of refraction lower than the aluminum nitride. The waveguide 1100 may route optical communications between a chip 1108 and another chip 1110 on the PCB 1102. In some embodiments, the PCB 1102 may include a rigid board or a flexible board.

In some embodiments, both of the AIN thin film 1106 and the dielectric material 1104 may include aluminum nitride. However, the AIN thin film 1106 may include first nitrogen content with a higher concentration than second nitrogen content included in the dielectric material 104 so that the AIN thin film 1106 may have a higher index of refraction than the dielectric material 104. Thus, a waveguide may be formed by the AIN thin film 1106 and the dielectric material 1104 so that a light beam may be guided to propagate through the AIN thin film 1106.

FIG. 11B is a block diagram illustrating a side view of the example chip-to-chip optical communication routing through the waveguide 1100 of FIG. 11A, arranged in accordance with at least some embodiments described herein.

FIG. 12A is a block diagram illustrating a cross-sectional view of a waveguide 1200 formed by an example AIN substrate, arranged in accordance with at least some embodiments described herein. The AIN substrate may include a layer of high-frequency polymer 1206 (e.g., polyimide, kapton, or other suitable materials), a first AIN thin film 1202 disposed on top of the high-frequency polymer 1206, and a second AIN thin film 1204 embedded in the first AIN thin film 1202.

The first AIN thin film 1202 may include nitrogen content with a first concentration level, and the second AIN thin film 1204 may include nitrogen content with a second concentration level that may be higher than the first concentration level. As a result, the second AIN thin film 1204 may have a higher index of refraction than the first AIN thin film 1202 so that the waveguide 1200 (e.g., a trench waveguide) may be formed by the second AIN thin film 1204 and the first AIN thin film 1206. A light beam may be guided through the waveguide through the second AIN thin film 1204. For example, the first AIN thin film 1202 may include 30% of nitrogen (or another suitable level of nitrogen) with an index of refraction of 1.575 (or another suitable index of refraction). The second AIN thin film 1204 may include 80% of nitrogen (or another suitable level of nitrogen) with an index of refraction of 1.725 (or another suitable index of refraction). The cross section of the second thin film 1204 may have a dimension of 50 micrometers by 50 micrometers or of another suitable dimension.

FIG. 12B is a block diagram illustrating another cross-sectional view of the waveguide 1200 of FIG. 12A that routes a light beam 1226 from a laser 1222 to a photodiode 1224, arranged in accordance with at least some embodiments described herein. The waveguide 1200 formed by the AIN substrate of FIG. 12A may be disposed on top of a PCB substrate 1228 (e.g., a main substrate illustrated in FIGS. 6A-8). As illustrated in FIG. 12B, the first AIN thin film 1202 and the second AIN thin film 1204 with different indices of refraction may create reflective surfaces 1230 and 1232 for the light beam 1226.

The laser 1222 may include a vertical-cavity surface-emitting laser (VCSEL) or another suitable laser that may emit the light beam 1226. The light beam 1226 may travel to the second AIN thin film 1204 and then may be reflected by the reflective surface 1230 to change its propagation direction. The light beam 1226 may be guided through the second AIN thin film 1204 and reflected by the reflective surface 1232 to propagate to the photodiode 1224.

FIG. 12C is a graphic representation 1250 illustrating a simulation of light transmission through the waveguide 1200 of FIGS. 12A and 12B, arranged in accordance with at least some embodiments described herein. The light beam 1226 emitted from the laser 1222 of FIG. 12B may be reflected to propagate through the waveguide 1200 of FIGS. 12A and 12B, and may then be reflected to propagate to the photodiode 1224 of FIG. 12B.

FIG. 13 is a block diagram illustrating a cross-sectional view of an example Bragg grating 1300, arranged in accordance with at least some embodiments described herein. The Bragg grating 1300 may be formed with aluminum nitride, part of which may be etched out to form etch pitches (e.g., etch pitches 1302). An effective index of refraction may vary in an etched section where the etch pitches locate, causing the index of refraction to change periodically in a direction 1304. The etch pitches may be designed to reflect or transmit a wavelength.

In FIG. 13, the etch pitches 1302 and air between the etch pitches 1302 may create an optical grating such as a Bragg grating. Alternatively, the etch pitches 1302 may be formed by first AIN with a first nitrogen concentration level. Second AIN with a second nitrogen concentration level (e.g., lower than the first nitrogen concentration level) may be filled between the etch pitches 1302 so that the first AIN and the second AIN may form an optical grating.

FIG. 14 is a block diagram illustrating an example WDM device 1400 that includes distributed Bragg reflectors 1402 and 1404, arranged in accordance with at least some embodiments described herein. The WDM device 1400 may include a WDM filter. The distributed Bragg reflectors 1402 and 1404 may be formed by etched Bragg gratings similar or identical to the etched Bragg grating 1300 of FIG. 13. Using a focusing distributed Bragg reflector, a light beam may diverge in plane and be focused to a different output. Pitches of the distributed Bragg reflector may be adjusted to reflect an optical signal with a first wavelength while transmitting another optical signal with another wavelength to a next focusing distributed Bragg reflector.

For example, an input light beam 1406 may include optical signals with different wavelengths. The distributed Bragg reflector 1402 may be configured to reflect a first optical signal with a first wavelength while transmitting a second optical signal with a second wavelength. For example, the distributed Bragg reflector 1402 may reflect the first optical signal with the first wavelength at a first angle so that the first optical signal is a first output signal 1408 from the WDM device 1400. Meanwhile, the distributed Bragg reflector 1402 may transmit the second optical signal with the second wavelength to the distributed Bragg reflector 1404. The distributed Bragg reflector 1404 may be configured to reflect the second optical signal at a second angle so that the second optical signal is a second output signal 1410 from the WDM device 1400.

With combined reference to FIGS. 10-14, some embodiments described herein may include an optical waveguide. The optical waveguide may include a layer of high-frequency polymer, a first AIN thin film disposed on top of the layer of high-frequency polymer, and a second AIN thin film embedded in or surrounded by the first AIN thin film. The first AIN thin film may include nitrogen content with a first nitrogen concentration level and a first index of refraction. The second AIN thin film may include nitrogen content with a second nitrogen concentration level and a second index of refraction. The first nitrogen concentration level (e.g., 85%) may be lower than the second nitrogen concentration level (e.g., 90%), the first index of refraction may be lower than the second index of refraction, and the second AIN thin film may be embedded in the first AIN thin film to guide a light beam to propagate through the second AIN thin film. The first AIN thin film and the second AIN thin film may form a trench waveguide. Alternatively, a ridge waveguide may be formed.

In some embodiments, optical waveguides (trench or ridge waveguides) may be formed using: (1) selective doping of aluminum nitride with oxygen and/or nitrogen; and/or (2) etching the AIN to form etch pitches, with air left between the etch pitches or deposing different stoichiometric content between the etch pitches.

In some embodiments, the second AIN thin film may be selectively etched to form an etched Bragg grating configured to reflect or transmit an optical signal with a particular wavelength. Alternatively or additionally, the second AIN thin film may be selectively etched to form distributed Bragg reflectors that operate as a WDM filter.

FIG. 15 is a graphic representation 1500 illustrating an example relationship between optical transmission and photon energy for AIN and Al₂O₃, arranged in accordance with at least some embodiments described herein. FIG. 15 shows that AIN is highly transmissive and may be used to form waveguides.

FIG. 16 is a graphic representation 1600 illustrating effective permittivity curves for a circuit stack-up, arranged in accordance with at least some embodiments described herein. The circuit stack-up may include an AIN substrate disposed on top of a PCB substrate. Detail of the circuit stack-up is provided in Table 1 below.

TABLE 1 a circuit stack-up Angle, Layer Material Thickness Permeability, e Tan d Top-1 Aluminum  12 micrometers 9.2 0.0021 Nitride 2 Kapton Foil  25 micrometers 3.4 0.0018 3 MEG tron VI  98 micrometers 3.6 0.004 4 MEG tron VI 106 micrometers 3.6 0.004 5 MEG tron VI 148 micrometers 3.2 0.004 Bottom-6 MEG tron VI 150 micrometers 3.5 0.004 The effective permittivity curves in FIG. 16 are simulated with the following parameters: a trace width between 45 micrometers and 55 micrometers, a trace thickness of 15 micrometers, and a trace length of 100 micrometers.

FIGS. 17A-17E illustrate example infrared (IR) thermal scans using a quantum focus instrument (QFI) IR camera microscope. FIG. 17A is a graphic representation 1700 illustrating an example thermal scan of a heat load on a kapton side, arranged in accordance with at least some embodiments described herein. The heat load may include a load of 0.3 A/3V. Heat generated by the heat load is generally not able to spread out laterally. For example, the heat is not able to spread out in an x-y plane such as a plane of the drawing sheet.

FIG. 17B is a graphic representation 1710 illustrating an example thermal scan of a heat load on an AIN substrate, arranged in accordance with at least some embodiments described herein. The heat load may include a load of 0.3 A/3V. The AIN substrate may include an AIN thin film with a thickness of 9 micrometers and a kapton foil with a thickness of 25 micrometers on a 3 millimeter (mm) by 3 mm sample resistor pack. FIG. 17B shows that heat generated by the heat load is generally able to spread out laterally with the AIN substrate for a faster dissipation, compared to the thermal simulation of FIG. 17A with kapton only. In some embodiments, it may only take a few milliseconds for the heat to spread out laterally through the AIN substrate.

FIG. 17C is a graphic representation 1720 illustrating an example thermal scan of a heat load on an FR4 substrate of a PCB, arranged in accordance with at least some embodiments described herein. The heat load may include a load of 0.3 A/1V. Heat generated by the heat load is generally not able to spread out laterally. For example, the heat is not able to spread out in an x-y plane such as a plane of the drawing sheet.

FIG. 17D is a graphic representation 1730 illustrating an example thermal scan of a heat load on a silver plated PCB substrate, arranged in accordance with at least some embodiments described herein. The heat load may include a load of 0.3 A/1V. Compared to the thermal simulation of FIG. 17C, heat generated by the heat load is able to spread out more widely for a faster dissipation than that of FIG. 17C.

FIG. 17E is a graphic representation 1740 illustrating an example thermal scan of a heat load on an AIN substrate, arranged in accordance with at least some embodiments described herein. The heat load may include a load of 0.5 A/3V. The AIN substrate may include an AIN thin film with a thickness of 13 micrometers and a kapton foil with a thickness of 25 micrometers. FIG. 17E shows that heat generated by the heat load is generally able to spread out laterally with the AIN substrate for a faster dissipation, compared to the thermal simulation of FIG. 17C with the FR4 substrate and the thermal simulation of FIG. 17D with silver plating.

FIG. 18 is a graphic representation 1800 illustrating example relationship between photon energy and an absorption coefficient α for Aluminum nitride, arranged in accordance with at least some embodiments described herein.

FIG. 19 is a graphic representation 1900 illustrating example relationship between an index of refraction and a wavenumber and example relationship between an absorption index and the wavenumber for Aluminum nitride, arranged in accordance with at least some embodiments described herein.

The present disclosure is not to be limited in terms of the particular embodiments described herein, which are intended as illustrations of various aspects. Many modifications and variations can be made without departing from its spirit and scope, as will be apparent to those skilled in the art. Functionally equivalent methods and apparatuses within the scope of the disclosure, in addition to those enumerated herein, will be apparent to those skilled in the art from the foregoing descriptions. Such modifications and variations are intended to fall within the scope of the appended claims. The present disclosure is to be limited only by the terms of the appended claims, along with the full scope of equivalents to which such claims are entitled. It is to be understood that the present disclosure is not limited to particular methods, reagents, compounds, compositions, or biological systems, which can, of course, vary. It is also to be understood that the terminology used herein is for the purpose of describing particular embodiments only, and is not intended to be limiting.

With respect to the use of substantially any plural and/or singular terms herein, those having skill in the art can translate from the plural to the singular and/or from the singular to the plural as is appropriate to the context and/or application. The various singular/plural permutations may be expressly set forth herein for sake of clarity.

The present invention may be embodied in other specific forms without departing from its spirit or essential characteristics. The described embodiments are to be considered in all respects only as illustrative and not restrictive. The scope of the invention is, therefore, indicated by the appended claims rather than by the foregoing description. All changes which come within the meaning and range of equivalency of the claims are to be embraced within their scope. 

What is claimed is:
 1. A printed circuit board, comprising: a main substrate that includes a signal path, wherein the signal path on the printed circuit board is parallel with an aluminum nitride (AlN) substrate; and the AlN substrate comprising: a metallization of silver-based deposition; a first heat spreader forming a first lateral thermal dissipation path oriented parallel with the signal path on the printed circuit board, the first heat spreader comprising a first AlN thin film having a first layer of high-frequency polymer as a carrier substrate atop a first layer of graphite foil; a second heat spreader forming a second lateral thermal dissipation path oriented parallel with the signal path on the printed circuit board, the second heat spreader comprising a second layer of graphite foil atop a second AlN thin film having a second layer of high-frequency polymer as a carrier substrate; and an AlN core positioned between the first heat spreader and the second heat spreader; wherein the first heat spreader and the second heat spreader are oriented parallel with one another on opposite sides of the AlN core such that the first layer of graphite foil sits atop the AlN core and the AlN core sits atop the second layer of graphite foil; and; and wherein the AlN substrate is bonded to the main substrate that includes one or more additional layers of the printed circuit board.
 2. The printed circuit board of claim 1, wherein the AlN substrate further comprises a first via coupled to a second via in the main substrate through a conductive path in a thermosetting conductive bonding film.
 3. The printed circuit board of claim 1, wherein the first AlN thin film includes nitrogen content and is free of fiber weave materials.
 4. The printed circuit board of claim 1, wherein the AlN substrate further comprises a first loss tangent that is lower than a second loss tangent of fiber weave materials.
 5. The printed circuit board of claim 1, wherein the AlN substrate has a thickness between 1 micrometer and 100 micrometers.
 6. The printed circuit board of claim 1, wherein the layer of high-frequency polymer comprises one of polyimide and kapton.
 7. The printed circuit board of claim 1, wherein each of the first heat spreader and the second heat spreader of the (AlN) substrate permits lateral spread of heat to avoid loss of routing space within the printed circuit board.
 8. The printed circuit board of claim 1, wherein the AlN substrate further comprises an optical waveguide included in at least a portion of the AlN substrate surrounded by dielectric material with an index of refraction different from the first AlN thin film.
 9. The printed circuit board of claim 1, wherein the AlN substrate further comprises a metallization of one of nickel (Ni)-based deposition, palladium-based deposition, Ni-chrome-electro-vacuum deposition, Tin palladium colloid electro less deposition, and Ni—P electro less deposition.
 10. The printed circuit board of claim 1, wherein the AlN substrate further comprises a stack-up of the (AlN) thin film, the first layer of high-frequency polymer, and one or more of a plating, a first patterned mask, a layer of electrolytic copper, a layer of metal deposition, a second patterned mask, or a layer of cladding copper.
 11. The printed circuit board of claim 10, wherein the AlN stack-up comprises the plating and the plating includes electro less nickel electro less palladium immersion gold (ENEPIG) plating.
 12. The printed circuit board of claim 1, wherein the AlN substrate is at least partially transparent.
 13. The printed circuit board of claim 1, further comprising at least one micro strip line deposited on the AlN substrate, the micro strip line comprising a trace width between 10 micrometers to 65 micrometers and a trace pitch width between 15 micrometers to 200 micrometers.
 14. An aluminum nitride AlN substrate suitable for use as a first layer of a printed circuit board, comprising: a metallization of silver-based deposition; a layer of cladding copper; an AlN thin film disposed on top of the layer of cladding copper; a layer of high-frequency polymer disposed on top of the AlN thin film; and a heat spreader forming a lateral thermal dissipation path, the thermal dissipation path parallel to a plane defined by the AlN substrate, the heat spreader further comprising at least a layer of graphite foil parallel to the AlN thin film; wherein the AlN substrate is bonded to a main substrate that includes one or more additional layers of the printed circuit board. 